BLUE ORIGIN

Sep 30, 2026

PLL IC Design Engineer - TeraWave

United States

Cupertino, California, United States · San Diego, California, United States · Seattle, Washington, United States · California, United States

About the opportunity

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

Special Mentions

Relocation provided

Travel expected up to 10% of the time

Interviews will include a technical assessment

This role will be based onsite in San Diego, CA; Bay Area, CA; or Renton, WA.

A temporary remote work exception is approved while our Bay Area and San Diego sites are being developed.

Base Pay Range for: CA applicants is $230,398.00 - $322,556.85 WA applicants is $230,398.00 - $322,556.85

Other site ranges may differ

Culture Statement

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.

Export Control Regulations

Applicants for employment at Blue Origin must be a U.S. citizen or national, U.S. permanent resident (i.e. current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Background Check

Required for all positions: Blue’s Standard Background Check

Required for Certain Job Profiles: Defense Biometric Identification System (DBIDS) background check if at any time the role requires one to be on a military installation

Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs. and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing, vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training.

Required for certain Job Profiles: Ability to obtain and maintain Merchant Mariner Credential, which includes pre-employment and random drug testing as well as DOT physical

Equal Employment Opportunity

Blue Origin is proud to be an Equal Opportunity/Affirmative Action Employer and is committed to attracting, retaining, and developing a highly qualified and dedicated work force. Blue Origin hires and promotes people on the basis of their qualifications, performance, and abilities. We support the establishment and maintenance of a workplace that fosters trust, equality, and teamwork. We provide all qualified applicants for employment and employees with equal opportunities for hire, promotion, and other terms and conditions of employment, regardless of their race, color, religion, sex, sexual orientation, gender identity, national origin/ethnicity, age, physical or mental disability, genetic factors, military/veteran status, or any other status or characteristic protected by federal, state, and/or local law. Blue Origin will consider for employment qualified applicants with criminal histories in a manner consistent with applicable federal, state, and local laws, including the Washington Fair Chance Act, the California Fair Chance Act, the Los Angeles Fair Chance in Hiring Ordinance, and other applicable laws. For more information on “Know Your Rights,” please see here eeoc.gov/poster.

Affirmative Action and Disability Accommodation

Applicants wishing to receive information on Blue Origin’s Affirmative Action Plans, or applicants requiring a reasonable accommodation in order to participate in the application and/or interview process, please contact us at EEOCompliance@blueorigin.com [EEOCompliance@blueorigin.com]. Please note this is a publicly managed inbox. Please do not include any personal medical information in your request.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

We are seeking an IC Design Engineer to work on the development of integrated Phase-Locked Loops (PLLs) and clocking systems in advanced CMOS/SiGe processes. This role is essential for advancing our technology offerings in space communication systems. You will be responsible for delivering state-of-the-art performance while contributing to innovative solutions that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.

Responsibilities include but are not limited to

Owning the system and circuit design of PLLs and clock distribution circuits in advanced CMOS technologies, focusing on performance optimization and trade-off analysis (phase noise / jitter, power, etc.).

Utilizing full proficiency in Spectre and AMS flows to develop high-performance PLL circuits.

Collaborating with RF and SOC system architects and chip leads to define requirements for PLLs and their sub-blocks based on system specifications.

Overseeing layout, top-level integration, floorplanning, and verification of the overall design for successful tape-out cycle.

Working closely with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and ensure reliable & high-yield production cycles.

Investigating and implementing fundamental analog building blocks to enhance overall circuit performance

Mentoring junior engineers for best design practices in analog domain.

Minimum requirements

Minimum Qualifications

Bachelor's degree in Electrical Engineering, or related technical discipline

7+ years of experience in the design and development of fractional-N PLLs, DLLs, and their sub-circuits in FinFET CMOS nodes such as 7n or more advanced.

Extensive experience in the design of PLL building blocks such as VCOs, high-speed integer and frac-N pre-scalers, PFDs, charge-pumps, etc.

Experience with clock domain synchronization techniques within systems involving multiple PLLs and/or clock domains.

Experience with clock distribution circuit design techniques and optimization, including clock trees, frequency multipliers and dividers, CML buffers, inductive peaking, etc.

Full proficiency in mixed-mode modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS.

Extensive experience in PLL silicon characterization and debugging.

Proficiency in the design of fundamental analog/RF building blocks, including amplifiers, filters, clock buffers, and bias generators.

Must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Preferred Qualifications

Advanced degree (MS/PhD) in Electrical Engineering related technical discipline

Strong expertise in loop design for phase noise/jitter, spur profile, area, and power optimization.

Experience designing All-Digital PLLs (ADPLL) and or sub-sampling PLLs is a plus.

Experience with fundamental analog building blocks such as LDOs, and operational amplifiers.

Fundamental understanding of device physics for process selection and performance optimization.

Familiarity with digital design, digital verification, and SystemVerilog modeling.

Benefits

Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.

Stock Options for all regular employees (working at least 20 hours/week)

Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.

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