NoC Interconnect Design Engineer and Architect

Job Area: Engineering Group, Engineering Group > ASICS Engineering

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Summary: The NoC bus team group consists of a multi-disciplinary group involved from early product specification and analysis effort to final RTL delivery to the SoCs. One aspect of the process is to identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best power interconnect.

Candidates should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design, and successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment.

The successful applicant will be responsible for creating micro-architecture bus components specifications as well as analyzing the performance results, deliver RTL and run tool flows.

Responsibilities also include evaluating new IPs, driving new protocol deployments as well as defining system wide guidelines for IPs to inter-operate together in the SoC.

Candidate should also be able to deliver RTL to the SoC team, support verification and silicon validation teams, and work with SW teams to support successful deployments of the interconnects.

Minimum

$121,800.00 - $182,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.